////////////////////////////////////
//file: timer.v
//Author: Qyw
///////////////////////////////////

module timer(//input
			clk_1m,
			rst_n,
			oe,
			//output
			check_over,
			time_out,
            time_20ms
			);

input		clk_1m,
			rst_n,
			oe;

output		check_over,
			time_out,
            time_20ms;

reg		[16:0]	cnt;

assign check_over = cnt == 17'd32767;
assign time_out = cnt == 17'b1111_1111_1111_1111_1;
assign time_20ms = cnt == 15'b100_1110_0010_0000;



always @(posedge clk_1m or negedge rst_n)
	if(~rst_n)
		cnt <= 17'd0;
	else if(~oe)
		cnt <= 17'd0;
	else
		cnt <= cnt + 1'b1;

endmodule
